As the battery size of electronic devices is getting smaller and smaller and the voltage is getting lower and lower, the requirements for a working efficiency of the switching mode power supply are getting higher and higher. Various techniques have been applied in the technology of the switching mode power supply to increase the efficiency. Among them, regarding the synchronous rectification technique, a metal oxide semiconductor field effect transistor (MOSFET) with a low on-state voltage drop is used to realize the rectification instead of the traditional diode, so as to reduce the conduction loss of the switching mode power supply system and improve the conversion efficiency of the switching mode power supply system. Since the MOSFET does not have the characteristic of unidirectional conduction as the diode does, it is necessary to insert a dead time between the on and off switching of the upper power transistor and the lower power transistor. During this dead time, both of the two transistors are turned off to avoid any damages to the power transistors.
A conventional dead time generating circuit with fixed dead time is shown in FIG. 1. The PWM signal is a pulse width modulation signal of the DC-DC converter, P_Ctrl is a gate drive logic signal of the upper power transistor, and N_Ctrl is a gate drive logic signal of the lower power transistor.
When the PWM is flipped from low level to high level, the P_Ctrl gets delayed by ten gate circuits including inverters INV9, INV1, INV2, INV3, INV4, NAD2, INV5, INV6 and INV7 and an NAND gate NAD1 to get flipped from low level to high level. While, the N_Ctrl to be flipped from high level to low level only gets delayed by five gate circuits including the inverters INV9, INV1, INV2, INV3 and the NAND gate NAD1. A time margin is formed between the rising edge of the P_Ctrl and the falling edge of the N_Ctrl.
Similarly, when the PWM is flipped from high level to low level, the rising edge of the N_Ctrl is delayed by nine gate circuits including NAND gates NAD2 and NAD1, and the inverters INV5, INV6, INV7, INV8, INV1, INV2, and INV3. While, the falling edge of the P_Ctrl is only delayed by four gate circuits including the NAND gate NAD2 and the inverters INV5, INV6, and INV7. Another time margin is formed between the falling edge of the P_Ctrl and the rising edge of the N_Ctrl. As being delayed by different numbers of gate circuits, a dead time is formed between the output signals of the N_Ctrl and P_Ctrl.
The advantage of the fixed dead time is the simplicity. The disadvantage of the fixed dead time is that the fixed dead time should be long enough to meet the need of avoiding shoot-through under different temperatures and different process corners, etc. Since the body diode of the synchronous rectifying transistor is turned on during the dead time, a large power consumption will be caused and the efficiency of the system will be affected by using the fixed dead time technique. Therefore, although the fixed dead time technique can prevent the power transistor from getting burnout, the dead time is not the optimal value, and the power consumption is large, thereby limiting the overall efficiency of the converter.